1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having sense amplifiers shared by adjacent memory banks.
2. Description of the Related Art
To take full advantage of an improvement in the operational speed of a central processing unit (CPU), the performance of a memory device storing information such as data and programs for the CPU should be correspondingly improved. However, the operational speeds of CPUs have improved so remarkably that the CPUs usually outperform conventional DRAMs, and the operational speed of the DRAM is often slower than the operational speed of the CPU. Multi-bank synchronous DRAMs, which include multiple banks and operate in synchronization with a system clock signal, have been developed to provide higher performance and overcome this problem.
Additionally, recent developments in multimedia applications have increasingly demanded semiconductor memory devices having large bandwidths, i.e., the capability to transmit a large amount of IO data per unit time. Accordingly, semiconductor memory devices having high bandwidths with 16, 32, 64, or more parallel bits have been developed. However, memory devices having a high bandwidth require many data lines for transmitting data. In particular, a double data rate synchronous DRAM, which outputs twice the amount of data per clock cycle, normally requires twice as many data lines. The increase in the number of data lines directly increases the area of a DRAM chip. Since the enlargement of the chip area increases the manufacturing cost, efficient data line use and layout are sought to reduce the chip area of a semiconductor memory device.